Experience: 3-12 Years
CTC: 5-30 LPA
Notice Period: Immediate Joiner or Max 30-45 days
DFT experience on SoC's with different scan techniques and multiple clock domains.
SCAN chain implementation/verification at chip and block level.
On chip compression techniques and ATE debug.
Exposure to DFT architecture/Methodology
ATPG vector generation and ATE debug
CMM Level 5 company-IT Service Based Company.