Physical Design Engineer
Experience: 2-15 Years
CTC: No Bar
Title :Physical Design Engineer
Experience: 2.5 - 15 Years
Desired Skills and Experience:
Handled Netlist to GDS II at block level for multiple tape outs.
Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm
Good knowledge of EDA tools from Synopsys , Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC
Hands-on experience in floor planning, placement optimizations, CTS and routing.
Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)
Exposure in physical implementation of timing/functional ECO’s
Good knowledge of VLSI process and device characteristics TCL, perl scripting.
SeviTech is an ASIC design company specializing in ASIC/SOC & FPGA services and solutions.
SeviTech Systems is the fastest growing Semiconductor Services and Solutions company based in Bangalore – Silicon Valley of India.
We are partnering with Silicon Valley, USA based radio design company headed by leading RF Chip architects from top 3 RF/Analog Chip Product companies. They are working on some of the most sought-after IoT radio designs and are growing rapidly to meet customer demand for their innovative designs.
We are currently engaged with several leading Semiconductor Companies, owning turn-key Design / Verification projects, in addition to providing services based on time and material model.
SeviTech has also developed and successfully deployed Verification Flows and many VIPs.
We are among top 5 service companies in India Semiconductor industry.
You can also visit : http://sevitechsystems.com/